1. Field of the Invention
This invention relates to digital data processing systems. More specifically, it relates to a new and improved memory arrangement for use in such a data processing system that increases the flexibility of memory references.
2. Description of the Prior Art
A digital data processing system comprises three elements: namely, a memory element, an input/output element and a processor element. The memory stores information in uniquely-identifiable addressable storage locations. This information includes data and instructions for processing the data. The processor unit transfers information to and from the memory element, interprets the information as either data or instructions, and processes the data in accordance with the instructions. The input/output element also communicates with the memory element in order to transfer data into the system and obtain processed data from it.
The memory element is typically connected to the processor element and the input/output element over one or more busses, which transfers a convenient number of bits of information in parallel. In various systems, eight, sixteen or thirty-two bits of information may be transferred between elements in parallel. The memory element stores this information in a location identified by an address. Often times, in addition to the information from the processor element or the input/output element, the memory element will also store additional bits of information that it generates itself for error checking or correction. This error checking or correction information is used by the memory element when the information is retrieved to determine if an error occurred between the time the information was stored and the time it was retrieved.
The memory element normally stores the entire block of information, plus the error checking or correction information, in one location, and retrieves the information from one location for transfer to the other elements. Thus, if the processor element, for example, desires to store information in only a portion of a location in memory, it must actually store information in the entire location. Furthermore, if the processor element desires to store information in portions of two adjacent locations, it must perform two transfers, with each transfer identifying each location. Similarly, if the processor desires to retrieve information from portions of two adjacent locations, it must perform two transfers, even if the bus could transfer all of the information in one transfer.
As a specific example, suppose the bus between the processor element and the memory element can transfer thirty-two bits of information in parallel, and the memory element stores thirty-two bits in each location, plus the error checking and correction information therefor. In prior arrangements, the processor could not retrieve bits of information stored in the sixteen most significant bits of one location and the sixteen least significant bits of the next higher location in one operation, even though the bus could transfer all thirty-two bits of information at once. Similarly, the processor could not, in one transfer over the bus, store thirty-two bits in the twenty-four most significant bits of one location and eight bits of a next higher adjacent location.
One reason for this inability in prior processors was that if the memory element did store information in only a portion of a memory location, then the error checking and correction information stored with the location would not be useful, as it is uniquely determined for the set of information bits in each location. It would be possible to have the memory element generate error correction or detection bits for each selected subgroup of information bits, but that would increase the complexity of the memory element to accommodate the additional bits that would be generated. However, requiring the processor to perform additional transfers also places additional overhead on the processor element, slowing its operation.